1. Field of the Invention
The present invention relates to the field of analog storage devices. More particularly, this invention relates to a circuit and method for controlling the application of programming voltages applied to non-volatile memory cells.
2. Description of Prior Art
Currently, various analog storage devices are designed with multiple column drivers, each responsible for applying programming voltage to a drain of a corresponding non-volatile memory cell or a corresponding column of nonvolatile memory cells situated in the analog storage device. As seen in conventional analog storage devices such as ISD1016.TM. sold by Information Storage Devices, Inc. of San Jose, Calif., assignee of the present invention, multiple column drivers are used for parallel programming of an array of nonvolatile memory cells as described in U.S. Pat. Nos. 5,220,531 and 5,623,436.
For example, as described in U.S. Pat. No. 5,623,436, conventional analog storage devices involve a complex, multi-iterative programming technique in which a plurality of column drivers are used to program a corresponding plurality of non-volatile (NV) memory cells. These column drivers share a common high voltage supply source which provides two bursts of voltage pulses to program multiple NV memory cells. As shown in FIG. 1, the first burst includes forty-five coarse pulses 110 which are monotonically increasing in voltage levels, starting at a voltage level which produces a weakly programmed memory cell and ending at a voltage level which produces a stronger programmed memory cell (ranging from 8-18 volts). The second burst includes ninety fine pulses 120 which are monotonically increasing in voltage level. However, the first fine pulse 121 starts at a voltage level of the last coarse pulse applied to the NV memory cell minus a step-back voltage (V.sub.stepback) 130. V.sub.stepback 130 is approximately two volts (2V). The fine pulse programming continues until the NV memory cell is programmed to a desired voltage level.
As shown in FIG. 2, each of the coarse pulses 110 (e.g., the first coarse pulse 111 of FIG. 1) is configured with a constant initial ramp rate 200 equal to 420 millivolts per microsecond (mV/.mu.s) until reaching a maximum voltage 210 associated with that coarse pulse 111. The pulse width of each coarse pulse, including pulse width 220 of first coarse pulse 111, is set to a constant time span preferably equal to 109 microseconds (.mu.s). Successive coarse pulses monotonically increase by a first incremental step voltage (V.sub.step1) 140 of 200 mV as shown in FIG. 1. This step voltage is required to cover a full voltage range of cell programming on a drain of the NV memory cell.
Each coarse pulse is initially applied to the corresponding NV memory cell and the content of that cell is subsequently read during a read operation in order to ascertain its present voltage level. Thereafter, the present voltage level is compared to a target voltage associated with an analog signal to be stored. If it is determined that an additional coarse pulse would place the NV memory cell at a voltage level greater than the target voltage (referred to as "over programming"), the remaining coarse pulses are not applied to the drain of the NV memory cell. This may be accomplished by temporarily disabling an interconnection between a voltage supply source and the drain of the NV memory cell. The remaining coarse pulses, however, will continue programming other NV memory cells.
Similar to coarse pulses 110, the fine pulses 120 of FIG. 1 are monotonically increasing in voltage; however, fine pulses 120 have an incremental voltage less than that associated with coarse pulses 110. As shown in FIG. 3, each fine pulse (e.g., first fine pulse 121 of FIG. 1) has an initial ramp rate 300 of 840 mV/.mu.s and a constant maximum voltage 310 being lower than the voltage of the final coarse pulse applied. The successive fine pulses are monotonically increasing by a second step voltage (V.sub.step2) 150 having an incremental step voltage of 22 mV as shown in FIG. 1. This enables more refined programming of the NV memory cell to increase resolution of analog storage playback. However, certain remaining fine pulses will not be applied to the drain of the NV memory cell once it is determined that an additional fine pulse would cause the NV memory cell to be over programmed.
In view of the above configuration, the number of column drivers required for parallel programming of NV memory cells is defined by the sampling rate together with the cell programming time. For example, for a sampling rate of 8 kilohertz (KHz) for a typical voice signal and a cell programming time of 12.5 ms, the number of column drivers required was approximately 100. Thus, cell programming occurs for 100 columns at a time.
It is contemplated, however, that this conventional programming scheme possess a number of disadvantages. For example, this scheme is quite complex and slow due to the step-by-step application of incremental programming voltages through a maximum of 45 coarse pulses and 90 fine pulses. In those situations where coarse pulses or fine pulses are generated but are not used during programming, the analog storage device is needlessly consuming power. Moreover, to support this conventional programming scheme, a substantial amount of additional circuitry is required such as a large number of column drivers. This additional circuitry poses a greater likelihood of device failure and an inefficient use of die area.